Datasheet

22.8.16 Channel Control A
Name: CHCTRLA
Offset: 0x40 + n*0x10 [n=0..31]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
THRESHOLD[1:0] BURSTLEN[3:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
TRIGACT[1:0]
Access
R/W R/W
Reset 0 0
Bit 15 14 13 12 11 10 9 8
TRIGSRC[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE SWRST
Access
R/W R/W R/W
Reset 0 0 0
Bits 29:28 – THRESHOLD[1:0] FIFO Threshold
These bits define the threshold from which the DMA starts to write to the destination. These bits have no
effect in the case of single beat transfers.
These bits are not enable-protected.
Value Name Description
0x0
1BEAT Destination write starts after each beat source addess read
0x1
2BEATS Destination write starts after 2-beats source address read
0x2
4BEATS Destination write starts after 4-beats source address read
0x3
8BEATS Destination write starts after 8-beats source address read
Bits 27:24 – BURSTLEN[3:0] Burst Length
These bits define the burst mode.
These bits are not enable-protected.
Value Name Description
0x0
SINGLE Single-beat burst
0x1
2BEAT 2-beats burst length
0x2
3BEAT 3-beats burst length
0x3
4BEAT 4-beats burst length
0x4
5BEAT 5-beats burst length
0x5
6BEAT 6-beats burst length
0x6
7BEAT 7-beats burst length
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 432