Datasheet

22.8.14 Descriptor Memory Section Base Address
Name: BASEADDR
Offset: 0x34
Reset: 0x00000000
Property: PAC Write Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
BASEADDR[31:24]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
BASEADDR[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
BASEADDR[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BASEADDR[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – BASEADDR[31:0] Descriptor Memory Base Address
These bits store the Descriptor memory section base address. The value must be 128-bit aligned.
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 430