Datasheet

22.8.12 Pending Channels
Name: PENDCH
Offset: 0x2C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
PENDCH31 PENDCH30 PENDCH29 PENDCH28 PENDCH27 PENDCH26 PENDCH25 PENDCH24
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PENDCH23 PENDCH22 PENDCH21 PENDCH20 PENDCH19 PENDCH18 PENDCH17 PENDCH16
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PENDCH15 PENDCH14 PENDCH13 PENDCH12 PENDCH11 PENDCH10 PENDCH9 PENDCH8
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
30, 31 – PENDCH Pending Channel n [n=31..0]
This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is
started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details
on trigger action settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on DMA channel n.
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 428