Datasheet

Table Of Contents

Bit 8 – TERR Transfer Error

This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Error

interrupt.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag

Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID).

Bits 4:0 – ID[4:0] Channel ID

These bits store the lowest channel number with pending interrupts. The number is valid if Suspend

(SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is

refreshed when a new channel (with channel number less than the current one) with pending interrupts is

detected, or when the application clears the corresponding channel interrupt sources. When no pending

channels interrupts are available, these bits will always return zero value when read.

When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.

SAM D5x/E5x Family Data Sheet

DMAC – Direct Memory Access Controller

Datasheet

DS60001507E-page 425