Datasheet

22.8.9 Interrupt Pending
Name: INTPEND
Offset: 0x20
Reset: 0x0000
Property: -
This register allows the user to identify the lowest DMA channel with pending interrupt.
An interrupt that handles several channels should consult the INTPEND register to find out which channel
number has priority (ignoring/filtering each channel that has its own interrupt line). An interrupt dedicated
to only one channel must not use the INTPEND register.
Bit 15 14 13 12 11 10 9 8
PEND BUSY FERR CRCERR SUSP TCMPL TERR
Access
R R R R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ID[4:0]
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 15 – PEND Pending
This bit will read '1' when the channel selected by Channel ID field (ID) is pending.
Bit 14 – BUSY Busy
This bit will read '1' when the channel selected by Channel ID field (ID) is busy.
Bit 13 – FERR Fetch Error
This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor.
Bit 12 – CRCERR CRC Error
This bit will read '1' when the channel selected by Channel ID field (ID) has a CRC Error Status Flag bit
set, and is set when the CRC monitor detects data corruption.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag
Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID).
Bit 10 – SUSP Channel Suspend
This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag
Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID).
Bit 9 – TCMPL Transfer Complete
This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete
interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag
Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID).
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 424