Datasheet

22.8.8 Priority Control 0
Name: PRICTRL0
Offset: 0x14
Reset: 0x40404040
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
RRLVLEN3 QOS03[1:0] LVLPRI3[4:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
RRLVLEN2 QOS02[1:0] LVLPRI2[4:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RRLVLEN1 QOS01[1:0] LVLPRI1[4:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RRLVLEN0 QOS00[1:0] LVLPRI0[4:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 0 0 0 0 0 0
Bits 7, 15, 23, 31 – RRLVLEN Level Round-Robin Scheduling Enable
For details on arbitration schemes, refer to 22.6.2.4 Arbitration.
Value Description
0
Static arbitration scheme for channels with level 0 priority.
1
Round-robin arbitration scheme for channels with level 0 priority.
Bits 5:6, 13:14, 21:22, 29:30 – QOS Level Quality of Service QoS Name Description 0x0 DISABLE
Background (no sensitive operation) 0x1 LOW Sensitive to bandwidth 0x2 MEDIUM Sensitive to latency
0x3 Critical Latency Critical Latency
Bits 0:4, 8:12, 16:20, 24:28 – LVLPRI Level Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds
the channel number of the last DMA channel being granted access as the active channel with priority
level 0.
When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit
group is non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to
'0').
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 423