Datasheet

Table Of Contents

An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled.

The interrupt request remains active until the Interrupt flag is cleared, the interrupt is disabled, the DMAC

is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear Interrupt

flags. All interrupt requests are ORed together on system level to generate one combined interrupt

request to the NVIC.

The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with

pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to

determine which Interrupt condition is present for the corresponding channel. It is also possible to read

the Interrupt Pending register (INTPEND), which provides the lowest channel number with pending

interrupt and the respective Interrupt flags.

Note: Interrupts must be globally enabled for interrupt requests to be generated.

22.6.6 Events

The DMAC can generate the following output events:

• Channel (CH): Generated when a block transfer for a given channel has been completed, or when a

beat transfer within a block transfer for a given channel has been completed. Refer to Event Output

Selection for details.

Setting the Channel Event Output Enable bit (CHEVCTRLx.EVOE = 1) enables the corresponding output

event configured in the Event Output Selection bit group in the Block Transfer Control register

(BTCTRL.EVOSEL). Clearing CHEVCTRLx.EVOE = 0 disables the corresponding output event.

The DMAC can take the following actions on an input event:

• Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals

are enabled

• Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled

• Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled

• Channel Suspend Operation (SUSPEND): suspend a channel operation

• Channel Resume Operation (RESUME): resume a suspended channel operation

• Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition

• Increase Priority (INCPRI): increase channel priority

Setting the Channel Event Input Enable bit (CHEVCTRLx.EVIE = 1) enables the corresponding action on

input event. Clearing this bit disables the corresponding action on input event. Note that several actions

can be enabled for incoming events. If several events are connected to the peripheral, any enabled action

will be taken for any of the incoming events. For further details on event input actions, refer to Event Input

Actions.

Note: Event input and outputs are not available for every channel. Refer to the Features section for

more information.