Datasheet

– In the first list descriptor, set the destination address with the initial checksum value
(DSTADDR = CHKINIT)
– Set the transfer source address (SRCADDR)
– Set the block transfer count (BTCNT)
– Set the memory CRC monitor operation mode (CRCCTRL.CRCMODE = CRCMON)
– Enable optional interrupts
4. Enable the corresponding DMA channel (CHCTRLAn.ENABLE)
Figure 22-21. CRC Computation and Check with Single or Linked Transfers
List with Multiple Linked DescriptorsList with Single Descriptor
Notes :
Figures assumes that STEPSIZE is 0 (X1).
T o ease understanding, buffer base address is SRCADDR minus BTCNT ‘items’.
Descriptor 0
SRCADDR =
ADDR 1
CHKINIT
BTCTRL
DESCADDR=
0x00000000
BTCNT = N
Data ‘ 0’
Data ‘ N-2 ’
Source Memory
ADDR1
Desc of this buffer
Data ‘ 1 ’
outside
Transfer start address: ADDR1 - N
Descriptor n (last)
Descriptor 0
SRCADDR =
ADDR 2
CHKINIT
BTCTRL
DESCADDR
= next desc address
BTCNT = M
SRCADDR =
ADDR 1
DON’T CARE
BTCTRL
DESCADDR=
BTCNT = N
Data ‘ 0’
Data ‘ N-1’
Data ‘ N’
Source Memory
ADDR1
ADDR2
Desc of this buffer
Desc of this buffer
outside
outside
Transfer start address: ADDR1 - N
Transfer start address: ADDR2 - M
CRC Computation
CRC Computation
Data ‘ 1 ’
Data ‘ N+ 1 ’
0x4
0x8
0x0
0xc
0x2
0x4
0x8
0x0
0xc
0x2
0x4
0x8
0x0
0xc
0x2
Expected CRC
Data ‘ M-2 ’
Expected CRC
CRC Computation
0x00000000
22.6.4 DMA Operation
Not applicable.
22.6.5 Interrupts
The DMAC channels have the following interrupt sources:
• Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding
channel. Refer to 22.6.2.5 Data Transmission for details.
• Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an
invalid descriptor has been fetched. Refer to 22.6.2.9 Error Handling for details.
• Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to
22.6.3.3 Channel Suspend and 22.6.2.5 Data Transmission for details.
Each interrupt source has an Interrupt flag associated with it. The Interrupt flag in the Channel Interrupt
Flag Status and Clear (CHINTFLAG) register is set when the Interrupt condition occurs. Each interrupt
can be individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set register
(CHINTENSET=1), and disabled by setting the corresponding bit in the Channel Interrupt Enable Clear
register (CHINTENCLR=1).
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 399