Datasheet

22.6.3.10 Memory CRC Monitor
When enabled, it is possible to continuously check a a memory block data integrity by calculating and
checking the CRC checksum. The expected CRC checksum value must be located in the last memory
block location, as shown in the table below:
CRCCTRL.CRCPOLY CRCCTRL.CRCBEATSIZE Last Memory Block Byte
Locations Value (MSB
Byte First)
CHECKSUM Result
CRC-16 Byte Expected CRC[7:0]
Expected CRC[15:8]
0x00000000
Half-word
Word 0x00
0x00
Expected CRC[7:0]
Expected CRC[15:8]
CRC-32 Byte Expected CRC[31:24]
Expected CRC[23:16]
Expected CRC[15:8]
Expected CRC[7:0]
CRC Magic Number
(0x2144DF1C)
Half-word
Word
When the channel is enabled and the descriptor is fetched, the CRC Checksum register (CRCCHKSUM)
is reloaded with the initial checksum value (CHKINIT), stored in the DSTADDR location of the first
descriptor. The DMA read and calculate the checksum over the entire data from the source
address.When the checksum calculation is completed the DMA read the last beat from the memory, the
calculated CRC value from the CRC Checksum register is compared to zero or CRC magic number,
depending on CRC polynomial selection.
If the CHECKSUM does not match the comparison value the DMA channel is disabled, and both and the
CRC Error bit in the Channel n Status register (CHSTATUSn.CRCERR) and Transfer Error interrupt flag
(CHINTFLAGn.TERR) are set. If enabled, the Transfer Error interrupt is generated.
If the calculated checksum value matches the compare value, the Transfer Complete interrupt flag
(CHINTFLAGn.TCMPL) is set, optional interrupt is generated and the DMA will perform the following
actions, depending on the descriptor list settings:
• If the list has only one descriptor, the DMA will re-fetch the descriptor
• If the current descriptor is the last descriptor from the list, the DMA will fetch the first descriptor from
the list
When the fetch is completed, the DMA restarts the operations described above when new triggers are
detected.
In order to enable the memory CRC monitor, the following actions must be performed:
1. The CRC module must be set to be used with a DMA channel (CRCCTRL.CRCSRC)
2. Reserve memory space addresses to configure a descriptor or a list of descriptors
3. Configure each descriptor
– Set the next descriptor address (DESCADDR)
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 398