Datasheet

initial checksum value (CHKINIT) stored in the Block Transfer Destination Address register (DSTADDR).
The DMA read and calculate the checksum over the data from the source address.When the checksum
calculation is completed, the CRC value is stored in the CRC Checksum register (CRCCHKSUM), the
Transfer Complete interrupt flag is set (CHINTFLAGn.TCMPL) and optional interrupt is generated.
If linked descriptor is in the list (DESCADDR !=0), the DMA will fetch the next descriptor and CRC
calculation continues as described above. When the last list descriptor is executed, the channel is
automatically disabled.
In order to enable the memory CRC generation, the following actions must be performed:
1. The CRC module must be set to be used with a DMA channel (CRCCTRL.CRCSRC)
2. Reserve memory space addresses to configure a descriptor or a list of descriptors
3. Configure each descriptor:
– Set the next descriptor address (DESCADDR)
– Set the destination address with the initial checksum value (DSTADDR = CHKINIT) in the first
descriptior in a list
– Set the transfer source address (SRCADDR)
– Set the block transfer count (BTCNT)
– Set the memory CRC generation operation mode (CRCCTRL.CRCMODE = CRCGEN)
– Enable optional interrupts
4. Enable the corresponding DMA channel (CHCTRLAn.ENABLE)
The figure below shows the CRC computation slots and descriptor configuration when single or linked-
descriptors transfers are enabled.
Figure 22-20. CRC Computation with Single Linked Transfers
List with Multiple Linked DescriptorsList with Single Descriptor
Notes :
Figures assumes that STEPSIZE is 0 (X1)
T o ease understanding (buffer base address is SRCADDR minus BTCNT ‘items’).
Descriptor 0
SRCADDR =
ADDR 1
CHKINIT
BTCTRL
DESCADDR=
BTCNT = N
Data ‘ 0’
Data ‘ N-1’
Source Memory
ADDR1
Desc of this buffer
Data ‘ 1 ’
outside
Transfer start address: ADDR1 - N
Descriptor n (last)
Descriptor 0
SRCADDR =
ADDR 2
CHKINIT
BTCTRL
DESCADDR = next
desc
BTCNT = M
SRCADDR =
ADDR 1
DON’T CARE
BTCTRL
DESCADDR=
BTCNT = N
Data ‘ 0’
Data ‘ N-1’
Data ‘ N’
Data ‘ M-1’
Source Memory
ADDR1
ADDR2
Desc of this buffer
Desc of this buffer
outside
outside
Transfer start address: ADDR1 - N
Transfer start address: ADDR2 - M
CRC ComputationCRC Computation
Data ‘ 1 ’
Data ‘ N+ 1 ’
0x4
0x8
0x0
0xc
0x2
0x4
0x8
0x0
0xc
0x2
0x4
0x8
0x0
0xc
0x2
0x00000000
0x00000000
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 397