Datasheet

Figure 22-19. CRC Generator Block Diagram
168 8 32
Checksum
read
crc32
CRCCTRL
CHECKSUM
bit-reverse +
complement
CRC-16 CRC-32
DMAC
Channels
CRCDATAIN
CRC on
DMA
data
CRC-16 or CRC-32 calculations can be performed on data passing through any DMA
channel. Once a DMA channel is selected as the source, the CRC engine will continuously
generate the CRC on the data passing through the DMA channel. The checksum is available
for readout once the DMA transaction is completed or aborted. A CRC can also be generated
on SRAM, Flash, or I/O memory by passing these data through a DMA channel. If the latter is
done, the destination register for the DMA data can be the data input (CRCDATAIN) register in
the CRC engine.
CRC using the I/O
interface
Before using the CRC engine with the I/O interface, the application must set the
CRC Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE).
8/16/32-bit bus transfer type can be selected.
CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the
data to the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the
register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to
the CRCDATAIN register the CRC engine takes four cycles to calculate the CRC. The CRC complete is
signaled by a set CRCBUSY bit in the CRCSTATUS register. New data can be written only when
CRCBUSY flag is not set.
22.6.3.9 Memory CRC Generation
When enabled, it is possible to automatically calculate a memory block checksum. When the channel is
enabled and the descriptor is fetched, the CRC Checksum register (CRCCHKSUM) is reloaded with the
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 396