Datasheet

If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be
suspended, and the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be
set.
Note: Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to
be suspended, the internal suspend command will be ignored.
For more details on transfer descriptors, refer to section 22.6.2.3 Transfer Descriptors.
22.6.3.4 Channel Resume and Next Suspend Skip
A channel operation can be resumed by software by setting the Resume command in the Command bit
field of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the
channel operation resumes from where it previously stopped when the Resume command is detected.
When the Resume command is issued before the channel is suspended, the next suspend action is
skipped and the channel continues the normal operation.
Figure 22-11. Channel Suspend/Resume Operation
CHENn
Memory Descriptor
Transfer
Resume Command
Descriptor 0
(suspend disabled)
Fetch
Block
Transfer 0
Descriptor 1
(suspend enabled)
Block
Transfer 1
Suspend skipped
Descriptor 2
(suspend enabled)
Block
Transfer 2
Channel
suspended
Descriptor 3
(last)
Block
Transfer 3
22.6.3.5 Event Input Actions
The event input actions are available only on the least significant DMA channels. For details on channels
with event input support, refer to the Event System documentation.
Before using event input actions, the event controller must be configured first according to the following
table, and the Channel Event Input Enable bit in the Channel Event Control register (CHEVCTRL.EVIE)
must be written to '1'. Refer also to 22.6.6 Events.
Table 22-1. Event Input Action
Action CHEVCTRL.EVACT CHCTRLA.TRIGSRC
None NOACT -
Normal Transfer TRIG DISABLE
Conditional Transfer on Strobe TRIG Any peripheral
Conditional Transfer CTRIG
Conditional Block Transfer CBLOCK
Channel Suspend SUSPEND
Channel Resume RESUME
Skip Next Block Suspend SSKIP
Increase priority INCPRI
Normal Transfer
The event input is used to trigger a beat or burst transfer on peripherals.
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 390