Datasheet

7. Go to step 4 if needed.
22.6.3.1.3 Adding a Descriptor Between Existing Descriptors
To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently
executed by the DMA must be identified.
1. If DMA is executing descriptor B, descriptor C cannot be inserted.
2. If DMA has not started to execute descriptor A, follow the steps:
2.1. Set the descriptor A VALID bit to '0'.
2.2. Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B.
2.3. Set the DESCADDR value of descriptor C to point to descriptor B.
2.4. Set the descriptor A VALID bit to '1'.
3. If DMA is executing descriptor A:
3.1. Apply the software suspend command to the channel and
3.2. Perform steps 2.1 through 2.4.
3.3. Apply the software resume command to the channel.
22.6.3.2 Transfer Quality of Service
Each priority level group has dedicated quality of service settings. The setting can be written in the
corresponding Quality of Service bit group in the Priority Control x register (PRICTRL0.QOSn).
Figure 22-10. Quality of Service
Transfer Trigger Channel 0
Transfer Trigger Channel 1
Active CH0 Active CH1 Active CH0 Active CH1
Fetch Operation
Data Transfer
Quality of Service Value
( QOS CH0 < QOS CH1)
CH0 CH1 CH0 CH1
QOS CH0 QOS CH1 QOS CH0 QOS CH1
When a channel is stored in the Pre-Fetch or Active Channel, the corresponding PRICTRLx.QOS bits
value is stored in the respective channel. As shown in Quality of Service, the DMAC will select the
highest QOS value between Active and Pre-Fetch channels. This value will apply to all DMAC buses.
22.6.3.3 Channel Suspend
The channel operation can be suspended at any time by software by writing a '1' to the Suspend
command in the Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing
burst transfer is completed, the channel operation is suspended and the suspend command is
automatically cleared.
When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register
is set (CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated.
By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control
register (BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed
a block transfer. The DMA channel will be kept enabled and will be able to receive transfer triggers, but it
will be removed from the arbitration scheme.
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 389