Datasheet

and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status
register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt is generated.
22.6.3 Additional Features
22.6.3.1 Linked Descriptors
A transaction can consist of either a single block transfer or of several block transfers. When a
transaction consists of several block transfers it is done with the help of linked descriptors.
Figure 22-3 illustrates how linked descriptors work. When the first block transfer is completed on DMA
channel 0, the DMAC fetches the next transfer descriptor, which is pointed to by the value stored in the
Next Descriptor Address (DESCADDR) register of the first transfer descriptor. Fetching the next transfer
descriptor (DESCADDR) is continued until the last transfer descriptor. When the block transfer for the last
transfer descriptor is executed and DESCADDR=0x00000000, the transaction is terminated. For further
details on how the next descriptor is fetched from SRAM, refer to section 22.6.2.5 Data Transmission.
22.6.3.1.1 Adding Descriptor to the End of a List
To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with
DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the
DESCADDR value of the current last descriptor to the address of the newly created descriptor.
22.6.3.1.2 Modifying a Descriptor in a List
In order to add descriptors to a linked list, the following actions must be performed:
1. Enable the Suspend interrupt for the DMA channel.
2. Enable the DMA channel.
3. Reserve memory space in SRAM to configure a new descriptor.
4. Configure the new descriptor:
– Set the next descriptor address (DESCADDR)
– Set the destination address (DSTADDR)
– Set the source address (SRCADDR)
– Configure the block transfer control (BTCTRL) including
• Optionally enable the suspend block action
• Set the descriptor VALID bit
5. Clear the VALID bit for the existing list and for the descriptor which has to be updated.
6. Read DESCADDR from the write-back memory.
– If the DMA has not already fetched the descriptor that requires changes (i.e., DESCADDR is
wrong):
• Update the DESCADDR location of the descriptor from the list
• Optionally clear the suspend block action
• Set the descriptor VALID bit to '1'
• Optionally enable the Resume Software command
– If the DMA is executing the same descriptor as the one that requires changes:
• Set the Channel Suspend Software command and wait for the suspend interrupt
• Update the next descriptor address (DESCRADDR) in the write-back memory
• Clear the interrupt sources and set the Resume Software command
• Update the DESCADDR location of the descriptor from the list
• Optionally clear the suspend block action
• Set the descriptor VALID bit to '1'
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 388