Datasheet

 = 

+  •  + 1 • 2

where BTCTRL.STEPSEL is zero
 = 

+  •  + 1 where BTCTRL.STEPSEL is one
• DSTADDR
START
is the destination address of the first beat transfer in the block transfer
• BTCNT is the initial number of beats remaining in the block transfer
• BEATSIZE is the configured number of bytes in a beat
• STEPSIZE is the configured number of beats for each incrementation
The following figure shows an example where DMA channel 0 is configured to increment destination
address by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination
address by two beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As
the source address for both channels are peripherals, source incrementation is disabled
(BTCTRL.SRCINC=0).
Figure 22-9. Destination Address Increment
DST Data Buffer
a
b
c
d
22.6.2.8 Internal FIFO
To improve the bandwidth, the DMAC can support FIFO operation. When single-beat burst configuration
is selected (CHCTRALx.BURSTLEN = SINGLE), the channel waits until the FIFO can transmit or accept
a single beat transfer before it requests a bus access to write to the destination address. In all other
cases, the channel waits until the FIFO threshold is reached before it requests a bus access to write to
the destination address. The threshold is configurable and can be set by writing the THRESHOLD bits in
the Channel x Control A register.
If the DMAC completes the read operations before the threshold is reached, the write to the destination is
automatically enabled. If the FIFO is empty and the read from source is ongoing, the DMA will wait again
until the FIFO threshold is reached before it requests a bus access to write the destination.
22.6.2.9 Error Handling
If a bus error is received from an AHB slave during a DMA data transfer, the corresponding active
channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt
Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is
generated. The transfer counter will not be decremented and its current value is written-back in the write-
back memory section before the channel is disabled.
When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and
the DMA fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding
channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 387