Datasheet

Figure 22-3. Memory Sections
Channel 0 – Descriptor n-1
Channel 0 – Last Descriptor
DESCADDR
DESCADDR
Device Memory Space
BASEADDR
Channel 0 – First Descriptor
Channel 1 – First Descriptor
Channel 2 – First Descriptor
Channel n – First Descriptor
Descriptor Section
WRBADDR Channel 0 Ongoing Descriptor
Channel 1 Ongoing Descriptor
Channel 2 Ongoing Descriptor
Channel n Ongoing Descriptor
Write-Back Section
Undefined
Undefined
Undefined
Undefined
Undefined
SRCADDR
DSTADDR
BTCTRL
DESCADDR
BTCNT
SRCADDR
DSTADDR
BTCTRL
DESCADDR
BTCNT
SRCADDR
DSTADDR
BTCTRL
0x00000000
BTCNT
The size of the descriptor and write-back memory sections are dependent on the number of the most
significant enabled DMA channel m, as shown below:
 = 128bits   + 1
For memory optimization, it is recommended to use the less significant DMA channels, if not all channels
are required.
The descriptor and write-back memory sections can either be two separate memory sections, or they can
share a memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections,
is that the same transaction for a channel can be repeated without having to modify the first transfer
descriptor. In addition, the latency from fetching the first descriptor of a transaction to the first burst
transfer is executed, is reduced.
22.6.2.4 Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer
request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the
queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending
Channels registers (PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter
will choose which DMA channel will be the next active channel. The next transfer descriptor will be
fetched from SRAM memory and stored internally in the Pre-Fetch Channel. The active channel is the
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 381