Datasheet

The following DMA channel bit is enable-protected, meaning that it can only be written when the
corresponding DMA channel is disabled:
• The Channel Software Reset bit in the Channel Control A (CHCTRLA.SWRST) register
The following CRC registers are enable-protected, that is, they can only be written when the CRC is
disabled (CRCCTRL.CRCSRC=0):
• The CRC Control (CRCCTRL) register
• CRC Checksum (CRCCHKSUM) register
Enable-protection is denoted by the ‘Enable-Protected’ property in the register description.
22.6.2.2 Enabling, Disabling, and Resetting
The DMAC is enabled by writing the DMA Enable bit in the Control (CTRL.DMAENABLE) register to '1'.
The DMAC is disabled by writing a '0' to the CTRL.DMAENABLE register.
A DMA channel is enabled by writing the Enable bit in the Channel Control A register
(CHCTRLA.ENABLE) to '1', after the corresponding channel ID to the channel is configured. A DMA
channel is disabled by writing a '0' to CHCTRLAn.ENABLE.
The CRC is enabled by writing a value to the CRC Source bits in the Control register
(CRCCTRL.CRCSRC). The CRC is disabled by writing a '0' to CRCCTRL.CRCSRC.
The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while
the DMAC and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial
state.
A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register
(CHCTRLAn.SWRST), after the corresponding channel is configured. The channel registers will be reset
to their initial state. The corresponding DMA channel must be disabled in order for the Reset to take
effect.
22.6.2.3 Transfer Descriptors
The transfer descriptors, together with the channel configurations, decide how a block transfer should be
executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one) and receives a
transfer trigger, its first transfer descriptor must be initialized and valid (BTCTRL.VALID). The first transfer
descriptor describes the first block transfer of a transaction.
All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section
Base Address (BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell
the DMAC where to find the descriptor memory section and the write-back memory section.
The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all
DMA channels. As BASEADDR points only to the first transfer descriptor of channel ‘0’ (see figure below).
All first transfer descriptors must be stored in a contiguous memory section, where the transfer
descriptors must be ordered according to their channel number. For further details on linked descriptors,
refer to 22.6.3.1 Linked Descriptors.
The write-back memory section is where the DMAC stores the transfer descriptors for the ongoing block
transfers. WRBADDR points to the ongoing transfer descriptor of channel ‘0’. All ongoing transfer
descriptors are stored in a contiguous memory section where the transfer descriptors are ordered
according to their channel number. The figure below shows an example of linked descriptors on DMA
channel ‘0’. For additional information on linked descriptors, refer to the 22.6.3.1 Linked Descriptors.
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 380