Datasheet

• Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control
register (CTRL.LVLENx=1)
DMA Channel Initialization
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must
be configured, as defined below:
• DMA Channel Configuration:
– The channel number of the DMA channel to configure must be written to the Channel Control A
(CHCTRLA) register.
– Trigger action must be selected by writing the Trigger Action bit field in the Channel Control A
(CHCTRLA.TRIGACT) register.
– Trigger source must be selected by writing the Trigger Source bit field in the Channel Control A
(CHCTRLA.TRIGSRC) register.
• Transfer Descriptor
– The size of each access of the data transfer bus must be selected by writing the Beat Size bit
group in the Block Transfer Control (BTCTRL.BEATSIZE) register.
– The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer
Control (BTCTRL.VALID) register.
– Number of beats in the block transfer must be selected by writing the Block Transfer Count
(BTCNT) register.
– Source address for the block transfer must be selected by writing the Block Transfer Source
Address (SRCADDR) register.
– Destination address for the block transfer must be selected by writing the Block Transfer
Destination Address (DSTADDR) register.
CRC Calculation
If CRC calculation is needed, the CRC engine must be configured before it is enabled, as described
below:
• The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control
(CRCCTRL.CRCSRC) register.
• The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the
CRC Control (CRCCTRL.CRCPOLY) register.
• If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit
group in the CRC Control (CRCCTRL.CRCBEATSIZE) register.
Register Properties
The following DMAC registers are enable-protected, that is, they can only be written when the DMAC is
disabled (CTRL.DMAENABLE=0):
• The Descriptor Base Memory Address (BASEADDR) register
• The Write-Back Memory Base Address (WRBADDR) register
The following DMAC bit is enable-protected, that is, it can only be written when the DMAC and CRC are
disabled (CTRL.DMAENABLE=0 and CRCCTRL.CRCSRC=0):
• The Software Reset bit in the Control (CTRL.SWRST) register
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 379