Datasheet

Figure 22-2. DMA Transfer Sizes
DMA transaction
Block transfer
Link Enabled
Burst transfer
Link EnabledLink Enabled
Beat transfer
• Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat
Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE)
• Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range
from 1 to 64k beats. A block transfer can be interrupted.
• Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to
the second and so forth, as shown in the figure above. A DMA transaction is the complete transfer of
all blocks within a linked list.
A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must
remain in SRAM. For further details on the transfer descriptor refer to 22.6.2.3 Transfer Descriptors.
The figure above shows several block transfers linked together, which are called linked descriptors. For
further information about linked descriptors, refer to 22.6.3.1 Linked Descriptors.
A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can
be configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers.
The transfer trigger will result in a DMA transfer request from the specific channel to the arbiter. If there
are several DMA channels with pending transfer requests, the arbiter chooses which channel is granted
access to become the active channel. The DMA channel granted access as the active channel will carry
out the transaction as configured in the transfer descriptor. A current transaction can be interrupted by a
higher prioritized channel, but will resume the block transfer when the according DMA channel is granted
access as the active channel again.
For each beat transfer, an optional output event can be generated. For each block transfer, optional
interrupts and an optional output event can be generated. When a transaction is completed, dependent of
the configuration, the DMA channel will either be suspended or disabled.
22.6.1.2 CRC
The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and
CRC-32 (IEEE 802.3). It can be used on a selectable DMA channel, or on the I/O interface. Refer to
22.6.3.8 CRC Operation for details.
22.6.2 Basic Operation
22.6.2.1 Initialization
DMAC Initialization
Before DMAC is enabled, it must be configured as defined below:
• The SRAM address of where the descriptor memory section is located must be written to the
Description Base Address (BASEADDR) register.
• The SRAM address of where the write-back section should be located must be written to the Write-
Back Memory Base Address (WRBADDR) register.
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 378