Datasheet

15.6.2.6 Peripheral Clock Masking
22.5.4 DMA
Not applicable.
22.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the
interrupt controller to be configured first.
Related Links
10.2 Nested Vector Interrupt Controller
22.5.6 Events
The events are connected to the event system.
22.5.7 Debug Operation
When the CPU is halted in Debug mode the DMAC will halt normal operation. The DMAC can be forced
to continue operation during debugging. Refer to 22.8.6 DBGCTRL for details.
22.5.8 Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller
(PAC), except for the following registers:
• Interrupt Pending register (INTPEND)
• Channel Interrupt Flag Status and Clear register (CHINTFLAG)
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
PAC write protection does not apply to accesses through an external debugger.
22.5.9 Analog Connections
Not applicable.
22.6 Functional Description
22.6.1 Principle of Operation
The DMAC consists of a DMA module and a CRC module.
22.6.1.1 DMA
The DMAC can transfer data between memories and peripherals without interaction from the CPU. The
data transferred by the DMAC are called transactions, and these transactions can be split into smaller
data transfers. The following figure shows the relationship between the different transfer sizes:
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 377