Datasheet

22.3 Block Diagram
Figure 22-1. DMAC Block Diagram
Descriptor
Fetch
HIGH SPEED
BUS MATRIX
AHB/APB
Bridge
AHB/APB
Bridge
Event System
Peripheral
Request / Ack
Event Input / Ack
Event Output
CPU
Write-back
Data
Transfer
Transfer
Control
Descriptor
Write-Back
Buffer
S
SS
M
M
SRAM
Interrupts
Arbiter
DMA Channels
Master
Interface
CRC Engine
n
Fetch
Engine
DMAC Internal Architecture
Channel 0
Channel n
Pre-Fetch
Channel
Data
Transfer
M
Fifo
Active
Channel
Optional
22.4 Signal Description
Not applicable.
22.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
22.5.1 I/O Lines
Not applicable.
22.5.2 Power Management
The DMAC will continue to operate in any Sleep mode where the selected source clock is running. The
DMAC’s interrupts can be used to wake-up the device from Sleep modes. Events connected to the event
system can trigger other operations in the system without exiting Sleep modes. On hardware or software
Reset, all registers are set to their Reset value.
Related Links
18. PM – Power Manager
22.5.3 Clocks
An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock can be configured in the
Main Clock peripheral (MCLK) before using the DMAC, and the default state of CLK_DMAC_AHB can be
found in the MCLK.AHBMASK register.
Related Links
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 376