Datasheet

– Single transfer using one descriptor
– Multi-buffer or circular buffer modes by linking multiple descriptors
• Up to 32channels
– Enable 32 independent transfers
– Automatic descriptor fetch for each channel
– Suspend/resume operation support for each channel
• Flexible arbitration scheme
– 4 configurable priority levels for each channel
– Fixed or round-robin priority scheme within each priority level
• From 1 to 256KB data transfer in a single block transfer
• Multiple addressing modes
– Static
– Configurable increment scheme
• Optional interrupt generation
– On block transfer complete
– On error detection
– On channel suspend
• 8 event inputs
– One event input for each of the 8 least significant DMA channels
– Can be selected to trigger normal transfers, periodic transfers or conditional transfers
– Can be selected to suspend or resume channel operation
• 4 event outputs
– One output event for each of the 4 least significant DMA channels
– Selectable generation on AHB, block, or transaction transfer complete
• Error management supported by write-back function
– Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer
• CRC polynomial software selectable to
– CRC-16 (CRC-CCITT)
– CRC-32 (IEEE
®
802.3)
SAM D5x/E5x Family Data Sheet
DMAC – Direct Memory Access Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 375