Datasheet

21.12.5 Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2)
Name: INTENSET
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 15 14 13 12 11 10 9 8
OVF TAMPER ALARM1 ALARM0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which
enables the Overflow interrupt.
Value Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 14 – TAMPER Tamper Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which
enables the Tamper interrupt.
Value Description
0
The Tamper interrupt it disabled.
1
The Tamper interrupt is enabled.
Bits 8, 9 – ALARMn Alarm n Interrupt Enable [n = 1..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Alarm n Interrupt Enable bit, which
and enables the Alarm n interrupt.
Value Description
0
The Alarm n interrupt is disabled.
1
The Alarm n interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable
bit, which enables the Periodic Interval n interrupt.
Value Description
0
Periodic Interval n interrupt is disabled.
1
Periodic Interval n interrupt is enabled.
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 359