Datasheet

21.12.2 Control B in Clock/Calendar mode (CTRLA.MODE=2)
Name: CTRLB
Offset: 0x2
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
ACTF[2:0] DEBF[2:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DMAEN RTCOUT DEBASYNC DEBMAJ GP2EN GP0EN
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 14:12 – ACTF[2:0] Active Layer Frequency
These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection
in terms of the CLK_RTC.
Value Name Description
0x0
DIV2 CLK_RTC_OUT = CLK_RTC / 2
0x1
DIV4 CLK_RTC_OUT = CLK_RTC / 4
0x2
DIV8 CLK_RTC_OUT = CLK_RTC / 8
0x3
DIV16 CLK_RTC_OUT = CLK_RTC / 16
0x4
DIV32 CLK_RTC_OUT = CLK_RTC / 32
0x5
DIV64 CLK_RTC_OUT = CLK_RTC / 64
0x6
DIV128 CLK_RTC_OUT = CLK_RTC / 128
0x7
DIV256 CLK_RTC_OUT = CLK_RTC / 256
Bits 10:8 – DEBF[2:0] Debounce Frequency
These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC.
Value Name Description
0x0
DIV2 CLK_RTC_DEB = CLK_RTC / 2
0x1
DIV4 CLK_RTC_DEB = CLK_RTC / 4
0x2
DIV8 CLK_RTC_DEB = CLK_RTC / 8
0x3
DIV16 CLK_RTC_DEB = CLK_RTC / 16
0x4
DIV32 CLK_RTC_DEB = CLK_RTC / 32
0x5
DIV64 CLK_RTC_DEB = CLK_RTC / 64
0x6
DIV128 CLK_RTC_DEB = CLK_RTC / 128
0x7
DIV256 CLK_RTC_DEB = CLK_RTC / 256
Bit 7 – DMAEN DMA Enable
The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register.
Value Description
0
Tamper DMA request is disabled. Reading TIMESTAMP has no effect on
INTFLAG.TAMPER.
1
Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER.
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 354