Datasheet

21.12.1 Control A in Clock/Calendar mode (CTRLA.MODE=2)
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
CLOCKSYNC GPTRST BKTRST PRESCALER[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MATCHCLR CLKREP MODE[1:0] ENABLE SWRST
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 15 – CLOCKSYNC CLOCK Read Synchronization Enable
The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent
reading valid values from the CLOCK register.
This bit is not enable-protected.
Value Description
0
CLOCK read synchronization is disabled
1
CLOCK read synchronization is enabled
Bit 14 – GPTRST GP Registers Reset On Tamper Enable
Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the
peripheral is disabled.
This bit is not synchronized.
Bit 13 – BKTRST BKUP Registers Reset On Tamper Enable
All BKUPn registers are affected. This bit can be written only when the peripheral is disabled.
This bit is not synchronized.
Value Description
0
BKUPn registers will not reset when a tamper condition occurs.
1
BKUPn registers will reset when a tamper condition occurs.
Bits 11:8 – PRESCALER[3:0] Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter
clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These
bits are not synchronized.
Value Name Description
0x0
OFF CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV1 CLK_RTC_CNT = GCLK_RTC/1
0x2
DIV2 CLK_RTC_CNT = GCLK_RTC/2
0x3
DIV4 CLK_RTC_CNT = GCLK_RTC/4
0x4
DIV8 CLK_RTC_CNT = GCLK_RTC/8
0x5
DIV16 CLK_RTC_CNT = GCLK_RTC/16
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 351