Datasheet

Separate debouncers are embedded for each external input. The debouncer for each input is enabled/
disabled with the Debounce Enable bits in the Tamper Control register (TAMPCTRL.DEBNCn). The
debouncer configuration is fixed for all inputs as set by the Control B register (CTRLB). The debouncing
period duration is configurable using the Debounce Frequency field in the Control B register
(CTRLB.DEBF). The period is set for all debouncers (i.e., the duration cannot be adjusted separately for
each debouncer).
When TAMPCTRL.DEBNCn = 0, INn is detected asynchronously. See Figure 21-5 for an example.
When TAMPCTRL.DEBNCn = 1, the detection time depends on whether the debouncer operates
synchronously or asynchronously, and whether majority detection is enabled or not. Refer to the table
below for more details. Synchronous versus asynchronous stability debouncing is configured by the
Debounce Asynchronous Enable bit in the Control B register (CTRLB.DEBASYNC):
• Synchronous (CTRLB.DEBASYNC = 0): INn is synchronized in two CLK_RTC periods and then must
remain stable for four CLK_RTC_DEB periods before a valid detection occurs. See Figure 21-6 for
an example.
• Asynchronous (CTRLB.DEBASYNC = 1): The first edge on INn is detected. Further detection is
blanked until INn remains stable for four CLK_RTC_DEB periods. See Figure 21-7 for an example.
Majority debouncing is configured by the Debounce Majority Enable bit in the Control B register
(CTRLB.DEBMAJ). INn must be valid for two out of three CLK_RTC_DEB periods. See Figure 21-8 for an
example.
Table 21-3. Debouncer Configuration
TAMPCTRL.
DEBNCn
CTRLB.
DEBMAJ
CTRLB.
DEBASYNC
Description
0 X X Detect edge on INn with no debouncing. Every edge
detected is immediately triggered.
1 0 0 Detect edge on INn with synchronous stability
debouncing. Edge detected is only triggered when INn
is stable for 4 consecutive CLK_RTC_DEB periods.
1 0 1 Detect edge on INn with asynchronous stability
debouncing. First detected edge is triggered
immediately. All subsequent detected edges are
ignored until INn is stable for 4 consecutive
CLK_RTC_DEB periods.
1 1 X Detect edge on INn with majority debouncing. Pin INn
is sampled for 3 consecutive CLK_RTC_DEB periods.
Signal level is determined by majority-rule (LLL, LLH,
LHL, HLL = '0' and LHH, HLH, HHL, HHH = '1').
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 294