Datasheet

21.6.8.2 Frequency Correction
The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-
slow or too-fast oscillator. Frequency correction requires that CTRLA.PRESCALER is greater than 1.
The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in
approximately 1ppm steps. Digital correction is achieved by adding or skipping a single count in the
prescaler once every 8192 CLK_RTC_OSC cycles. The Value bit group in the Frequency Correction
register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 128 of
these periods. The resulting correction is as follows:
Correctioninppm =
FREQCORR.VALUE
8192  128
 10
6
ppm
This results in a resolution of 0.95367ppm.
The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the
correction. A positive value will add counts and increase the period (reducing the frequency), and a
negative value will reduce counts per period (speeding up the frequency).
Digital correction also affects the generation of the periodic events from the prescaler. When the
correction is applied at the end of the correction cycle period, the interval between the previous periodic
event and the next occurrence may also be shortened or lengthened depending on the correction value.
21.6.8.3 Backup Registers
The RTC includes eight Backup registers (BKUPn). These registers maintain their content in Backup
sleep mode. They can be used to store user-defined values.
If more user-defined data must be stored than the eight Backup registers can hold, the General Purpose
registers (GPn) can be used.
Related Links
18. PM – Power Manager
21.6.8.4 General Purpose Registers
The RTC includes four General Purpose registers (GPn). These registers are reset only when the RTC is
reset or when tamper detection occurs while CTRLA.GPTRST=1, and remain powered while the RTC is
powered. They can be used to store user-defined values while other parts of the system are powered off.
The general purpose registers 2*n and 2*n+1 are enabled by writing a '1' to the General Purpose Enable
bit n in the Control B register (CTRLB.GPnEN).
The GP registers share internal resources with the COMPARE/ALARM features. Each COMPARE/
ALARM register have a separate read buffer and write buffer. When the general purpose feature is
enabled the even GP uses the read buffer while the odd GP uses the write buffer.
When the COMPARE/ALARM register is written, the write buffer hold temporarily the COMPARE/ALARM
value until the synchronisation is complete (bit SYNCBUSY.COMPn going to 0). After the write is
completed the write buffer can be used as a odd general purpose register whithout affecting the
COMPARE/ALARM function.
If the COMPARE/ALARM function is not used, the read buffer can be used as an even general purpose
register. In this case writing the even GP will temporarirely use the write buffer until the synchronisation is
complete (bit SYNCBUSY.GPn going to 0). Thus an even GP must be written before writing the odd GP.
Changing or writing an even GP needs to temporarily save the value of the odd GP.
Before using an even GP, the associated COMPARE/ALARM feature must be disabled by writing a '1' to
the General Purpose Enable bit in the Control B register (CTRLB.GPnEN). To re-enable the compare/
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 292