Datasheet

• Counter Value register, COUNT
• Clock Value register, CLOCK
• Counter Period register, PER
• Compare n Value registers, COMPn
• Alarm n Value registers, ALARMn
• Frequency Correction register, FREQCORR
• Alarm n Mask register, MASKn
• The General Purpose n registers (GPn)
The following registers are synchronized when read:
• The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA
(CTRLA.COUNTSYNC) is '1'
• The Clock Value register, CLOCK, if the Clock Read Sync Enable bit in CTRLA
(CTRLA.CLOCKSYNC) is '1'
• The Timestamp Value register (TIMESTAMP)
Required write synchronization is denoted by the "Write-Synchronized" property in the register
description.
Required read synchronization is denoted by the "Read-Synchronized" property in the register
description.
Related Links
13.3 Register Synchronization
21.6.8 Additional Features
21.6.8.1 Periodic Intervals
The RTC prescaler can generate interrupts and events at periodic intervals, allowing flexible system tick
creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an interrupt/event.
When one of the eight Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..7])
is '1', an event is generated on the 0-to-1 transition of the related bit in the prescaler, resulting in a
periodic event frequency of:

PERIODIC(n)
=

CLK_RTC_OSC
2
n+3
f
CLK_RTC_OSC
is the frequency of the internal prescaler clock CLK_RTC_OSC, and n is the position of the
EVCTRL.PEREOn bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles,
PER1 every 16 cycles, etc. This is shown in the figure below.
Periodic events are independent of the prescaler setting used by the RTC counter, except if
CTRLA.PRESCALER is zero. Then, no periodic events will be generated.
Figure 21-4. Example Periodic Events
CLK_RTC_OSC
PER0
PER1
PER2
PER3
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 291