Datasheet

21.6.5 Events
The RTC can generate the following output events:
• Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero.
• Tamper (TAMPER): Generated on detection of valid signal on a tamper input pin or tamper event
input.
• Compare (CMPn): Indicates a match between the counter value and the compare register.
• Alarm (ALARM): Indicates a match between the clock value and the alarm register.
• Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to 21.6.8.1 Periodic
Intervals for details.
• Periodic Daily (PERD): Generated when the COUNT/CLOCK has incremented at a fixed period of
time.
Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO=1) enables the corresponding
output event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS -
Event System for details on configuring the event system.
The RTC can take the following actions on an input event:
• Tamper (TAMPEVT): Capture the RTC counter to the timestamp register. See Tamper Detection.
Writing a one to an Event Input bit into the Event Control register (EVCTRL.xxxEI) enables the
corresponding action on input event. Writing a zero to this bit disables the corresponding action on input
event.
Related Links
31. EVSYS – Event System
21.6.6 Sleep Mode Operation
The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts
can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the
system without exiting the sleep mode.
An interrupt request will be generated after the wake-up if the Interrupt Controller is configured
accordingly. Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the
CPU will continue executing right from the first instruction that followed the entry into sleep.
The periodic events can also wake up the CPU through the interrupt function of the Event System. In this
case, the event must be enabled and connected to an event channel with its interrupt enabled. See Event
System for more information.
21.6.7 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in Control A register, CTRLA.SWRST
• Enable bit in Control A register, CTRLA.ENABLE
• Count Read Synchronization bit in Control A register (CTRLA.COUNTSYNC)
• Clock Read Synchronization bit in Control A register (CTRLA.COUNTSYNC)
The following registers are synchronized when written:
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 290