Datasheet

(INTFLAG.ALARMn, n=0..1) is set on the next 0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock
counter, it means the Alarm 0 Interrupt flag is set with a delay of 1s after the occurrence of alarm match.
A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm n Mask register
(MASKn.SEL). These bits determine which time/date fields of the clock and alarm values are valid for
comparison and which are ignored.
If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is set, the counter is cleared on
the next counter cycle when an alarm match with ALARMn occurs. This allows the RTC to generate
periodic interrupts or events with longer periods than it would be possible with the prescaler events only
(see 21.6.8.1 Periodic Intervals).
Note: When CTRLA.MATCHCLR is 1, INTFLAG.ALARM0 and INTFLAG.OVF will both be set
simultaneously on an alarm match with ALARMn.
21.6.3 DMA Operation
The RTC generates the following DMA request:
• Tamper (TAMPER): The request is set on capture of the timestamp. The request is cleared when the
Timestamp register is read.
If the CPU accesses the registers which are source for DMA request set/clear condition, the DMA request
can be lost or the DMA transfer can be corrupted, if enabled.
21.6.4 Interrupts
The RTC has the following interrupt sources:
• Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero.
• Tamper (TAMPER): Indicates detection of valid signal on a tamper input pin or tamper event input.
• Compare (CMPn): Indicates a match between the counter value and the compare register.
• Alarm (ALARMn): Indicates a match between the clock value and the alarm register.
• Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to 21.6.8.1 Periodic
Intervals for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1),
and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1).
An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is
enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is
disabled or the RTC is reset. See the description of the INTFLAG registers for details on how to clear
interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined
interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must
read the INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested
Vector Interrupt Controller for details.
Related Links
10.2 Nested Vector Interrupt Controller
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 289