Datasheet

The counter value is continuously compared with the 32-bit Compare registers (COMPn, n=0–1). When a
compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.CMPn) is set on the next 0-to-1 transition of CLK_RTC_CNT.
If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on
the next counter cycle when a compare match with COMPn occurs. This allows the RTC to generate
periodic interrupts or events with longer periods than the prescaler events. Note that when
CTRLA.MATCHCLR is '1', INTFLAG.CMPn and INTFLAG.OVF will both be set simultaneously on a
compare match with COMPn.
21.6.2.4 16-Bit Counter (Mode 1)
When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x1, the
counter operates in 16-bit Counter mode as shown in Figure 21-2. When the RTC is enabled, the counter
will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period
register (PER) holds the maximum value of the counter. The counter will increment until it reaches the
PER value, and then wrap to 0x0000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and
Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit
format.
The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0..). When a
compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.CMPn, n=0..) is set on the next 0-to-1 transition of CLK_RTC_CNT.
21.6.2.5 Clock/Calendar (Mode 2)
When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x2, the
counter operates in Clock/Calendar mode, as shown in Figure 21-3. When the RTC is enabled, the
counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC
prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode.
The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date
format. Time is represented as:
• Seconds
• Minutes
• Hours
Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the
Control A register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled.
The date is represented in this form:
• Day as the numeric day of the month (starting at 1)
• Month as the numeric month of the year (1 = January, 2 = February, etc.)
• Year as a value from 0x00 to 0x3F. This value must be added to a user-defined reference year. The
reference year must be a leap year (2016, 2020 etc). Example: the year value 0x2D, added to a
reference year 2016, represents the year 2061.
The RTC will increment until it reaches the top value of 23:59:59 December 31 of year value 0x3F, and
then wrap to 00:00:00 January 1 of year value 0x00. This will set the Overflow Interrupt flag in the
Interrupt Flag Status and Clear registers (INTFLAG.OVF).
The clock value is continuously compared with the 32-bit Alarm registers (ALARMn, n=0–1). When an
alarm match occurs, the Alarm n Interrupt flag in the Interrupt Flag Status and Clear registers
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 288