Datasheet

21.6.2 Basic Operation
21.6.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the RTC is disabled
(CTRLA.ENABLE=0):
• Operating Mode bits in the Control A register (CTRLA.MODE)
• Prescaler bits in the Control A register (CTRLA.PRESCALER)
• Clear on Match bit in the Control A register (CTRLA.MATCHCLR)
• Clock Representation bit in the Control A register (CTRLA.CLKREP)
The following registers are enable-protected:
• Control B register (CTRLB)
• Event Control register (EVCTRL)
• Tamper Control register (TAMPCTRL)
Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE=0).
If the RTC is enabled (CTRLA.ENABLE=1), these operations are necessary: first write
CTRLA.ENABLE=0 and check whether the write synchronization has finished, then change the desired
bit field value. Enable-protected bits in CTRLA register can be written at the same time as
CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
The RTC prescaler divides the source clock for the RTC counter.
Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter
for correct operation.
The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula:

CLK_RTC_CNT
=

CLK_RTC_OSC
2
PRESCALER
The frequency of the oscillator clock, CLK_RTC_OSC, is given by f
CLK_RTC_OSC
, and f
CLK_RTC_CNT
is the
frequency of the internal prescaled RTC clock, CLK_RTC_CNT.
21.6.2.2 Enabling, Disabling, and Resetting
The RTC is enabled by setting the Enable bit in the Control A register (CTRLA.ENABLE=1). The RTC is
disabled by writing CTRLA.ENABLE=0.
The RTC is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). All
registers in the RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The
RTC must be disabled before resetting it.
21.6.2.3 32-Bit Counter (Mode 0)
When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x0, the
counter operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 21-1. When
the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter
will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the
Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit
format.
SAM D5x/E5x Family Data Sheet
RTC – Real-Time Counter
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 287