Datasheet

20.8.8 Clear
Name: CLEAR
Offset: 0x0C
Reset: 0x00
Property: Write-Synchronized
Bit 7 6 5 4 3 2 1 0
CLEAR[7:0]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – CLEAR[7:0] Watchdog Clear
In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog
Timer and the watchdog time-out period is restarted.
In Window mode, any writing attempt to this register before the time-out period started (i.e., during
TO
WDTW
) will issue an immediate system Reset. Writing 0xA5 during the time-out period TO
WDT
will clear
the Watchdog Timer and the complete time-out sequence (first TO
WDTW
then TO
WDT
) is restarted.
In both modes, writing any other value than 0xA5 will issue an immediate system Reset.
SAM D5x/E5x Family Data Sheet
WDT – Watchdog Timer
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 282