Datasheet

20.8.2 Configuration
Name: CONFIG
Offset: 0x01
Reset: x initially determined from NVM User Row after reset
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
WINDOW[3:0] PER[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period
In Window mode, these bits determine the watchdog closed window period as a number of cycles of the
1.024kHz CLK_WDT_OSC clock.
These bits are loaded from NVM User Row at start-up.
Value Name Description
0x0
CYC8 8 clock cycles
0x1
CYC16 16 clock cycles
0x2
CYC32 32 clock cycles
0x3
CYC64 64 clock cycles
0x4
CYC128 128 clock cycles
0x5
CYC256 256 clock cycles
0x6
CYC512 512 clock cycles
0x7
CYC1024 1024 clock cycles
0x8
CYC2048 2048 clock cycles
0x9
CYC4096 4096 clock cycles
0xA
CYC8192 8192 clock cycles
0xB
CYC16384 16384 clock cycles
0xC-0xF
Reserved Reserved
Bits 3:0 – PER[3:0] Time-Out Period
These bits determine the watchdog time-out period as a number of 1.024kHz CLK_WDTOSC clock
cycles. In Window mode operation, these bits define the open window period.
These bits are loaded from NVM User Row at startup.
Value Name Description
0x0
CYC8 8 clock cycles
0x1
CYC16 16 clock cycles
0x2
CYC32 32 clock cycles
0x3
CYC64 64 clock cycles
0x4
CYC128 128 clock cycles
0x5
CYC256 256 clock cycles
0x6
CYC512 512 clock cycles
0x7
CYC1024 1024 clock cycles
0x8
CYC2048 2048 clock cycles
0x9
CYC4096 4096 clock cycles
0xA
CYC8192 8192 clock cycles
0xB
CYC16384 16384 clock cycles
SAM D5x/E5x Family Data Sheet
WDT – Watchdog Timer
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 275