Datasheet

20.7 Register Summary
Offset Name Bit Pos.
0x00 CTRLA 7:0 ALWAYSON WEN ENABLE
0x01 CONFIG 7:0 WINDOW[3:0] PER[3:0]
0x02 EWCTRL 7:0 EWOFFSET[3:0]
0x03 Reserved
0x04 INTENCLR 7:0 EW
0x05 INTENSET 7:0 EW
0x06 INTFLAG 7:0 EW
0x07 Reserved
0x08 SYNCBUSY
7:0 CLEAR ALWAYSON WEN ENABLE
15:8
23:16
31:24
0x0C CLEAR 7:0 CLEAR[7:0]
20.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 20.5.8 Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details,
refer to 20.6.7 Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
SAM D5x/E5x Family Data Sheet
WDT – Watchdog Timer
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 273