Datasheet

Table Of Contents

The user must take caution when programming the Early Warning Offset bits. If these bits define an Early

Warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out

system reset is generated prior to the Early Warning interrupt. Consequently, the Early Warning interrupt

will never be generated.

In window mode, the Early Warning interrupt is generated at the start of the open window period. In a

typical application where the system is in sleep mode, the Early Warning interrupt can be used to wake

up and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep

mode.

If the WDT is operating in Normal mode with CONFIG.PER = 0x2 and

EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16

CLK_WDT_OSC clock cycles after the start of the time-out period. The time-out system

reset is generated 32 CLK_WDT_OSC clock cycles after the start of the watchdog time-

out period.

SAM D5x/E5x Family Data Sheet

WDT – Watchdog Timer

Datasheet

DS60001507E-page 272