Datasheet

Table Of Contents

Figure 20-3. Window-Mode Operation

5 10 15 20 25 30 35

WDT Timeout

Early Warning Interrupt

Timely WDT Clear

t[ms]

WDT

System Reset

WDT Count

PER[3:0] = 0

WINDOW[3:0] = 0

WDTW

Early WDT Clear

Closed Open

20.6.3 DMA Operation

Not applicable.

20.6.4 Interrupts

The WDT has the following interrupt source:

• Early Warning (EW): Indicates that the counter is approaching the time-out condition.

– This interrupt is an asynchronous wake-up source.

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status

and Clear (INTFLAG) register is set when the interrupt condition occurs.

Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable

Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable

Clear (INTENCLR) register.

An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.

The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the

WDT is reset. See the 20.8.6 INTFLAG register description for details on how to clear interrupt flags. All

interrupt requests from the peripheral are ORed together on system level to generate one combined

interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt

condition is present.

Note: Interrupts must be globally enabled for interrupt requests to be generated.