Datasheet

Table Of Contents
20.3 Block Diagram
Figure 20-1. WDT Block Diagram
0xA5
CLEAR
COUNT
0
CLK_WDT_OSC
OSC32KCTRL
PER/WINDOWS/EWOFFSET
Early Warning Interrupt
Reset
20.4 Signal Description
Not applicable.
20.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
20.5.1 I/O Lines
Not applicable.
20.5.2 Power Management
The WDT can continue to operate in any sleep modes where the selected source clock is running. The
WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other
operations in the system without exiting sleep modes.
Related Links
18. PM – Power Manager
20.5.3 Clocks
The WDT bus clock (CLK_WDT_APB) can be enabled and disabled (masked) in the Main Clock module
(MCLK).
A 1.024 kHz oscillator clock (CLK_WDT_OSC) is required to clock the WDT internal counter.
The CLK_WDT_OSC CLOCK is sourced from the clock of the internal Ultra Low-Power Oscillator
(OSCULP32K). Due to ultra low-power design, the oscillator is not accurate, hence the exact time-out
period may vary from device-to-device. This variation must be considered when designing software that
uses the WDT to ensure that the time-out periods used are valid for all devices.
SAM D5x/E5x Family Data Sheet
WDT – Watchdog Timer
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 266