Datasheet

19.8.6 Voltage Regulator System (VREG) Control
Name: VREG
Offset: 0x18
Reset: 0x00000002
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
VSPER[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bit 23 22 21 20 19 18 17 16
VSEN
Access
R/W
Reset 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
RUNBKUP SEL ENABLE
Access
R/W R/W R/W
Reset 0 0 1
Bits 26:24 – VSPER[2:0] Voltage Scaling Period
This bitfield defines the time between the voltage steps when the VDDCORE voltage scaling is enabled.
The time is (2
VSPER
) * T, where T is an internal period (typ 250 ns).
Bit 16 – VSEN Voltage Scaling Enable
Value Description
0
The voltage scaling is disabled.
1
The voltage scaling is enabled.
Bit 7 – RUNBKUP Run in Backup
This bit controls how the main voltage regulator behaves in backup sleep mode.
Value Description
0
The main voltage regulator is halted during backup sleep mode.
1
The main voltage regulator is not stopped during backup sleep mode.
Bit 2 – SEL Voltage Regulator Selection
This bit is loaded from NVM User Row at start-up. Refer to NVM User Row Mapping section for more
details.
Value Description
0
The main voltage regulator is a LDO voltage regulator.
1
The main voltage regulator is a buck converter.
SAM D5x/E5x Family Data Sheet
SUPC – Supply Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 258