Datasheet

19.8.3 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x08
Reset: 0x0000010X
Property: -
In the reset value: X= determined from NVM User Row (0xX=0bx00y)
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
VCORERDY VREGRDY
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
B33SRDY BOD33DET BOD33RDY
Access
R/W R/W R/W
Reset 0 0 y
Bit 10 – VCORERDY VDDCORE Voltage Ready
This flag is cleared by writing a '1 to it.
This flag is set on a zero-to-one transition of the VDDCORE Ready bit in the Status register
(STATUS.VCORERDY) and will generate an interrupt request if INTENSET.VCORERDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the VCORERDY interrupt flag.
Bit 8 – VREGRDY Voltage Regulator Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the Voltage Regulator Ready bit in the Status register
(STATUS.VREGRDY) and will generate an interrupt request if INTENSET.VREGRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the VREGRDY interrupt flag.
Bit 2 – B33SRDY BOD33 Synchronization Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register
(STATUS.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the BOD33 Synchronization Ready interrupt flag.
SAM D5x/E5x Family Data Sheet
SUPC – Supply Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 251