Datasheet

19.8.2 Interrupt Enable Set
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
VCORERDY VREGRDY
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
B33SRDY BOD33DET BOD33RDY
Access
R/W R/W R/W
Reset 0 0 0
Bit 10 – VCORERDY VDDCORE Voltage Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the VDDCORE Ready Interrupt Enable bit, which enables the VDDCORE
Ready interrupt.
Value Description
0
The VDDCORE Ready interrupt is disabled.
1
The VDDCORE Ready interrupt is enabled and an interrupt request will be generated when
the VCORERDY Interrupt Flag is set.
Bit 8 – VREGRDY Voltage Regulator Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Voltage Regulator Ready Interrupt Enable bit, which enables the Voltage
Regulator Ready interrupt.
Value Description
0
The Voltage Regulator Ready interrupt is disabled.
1
The Voltage Regulator Ready interrupt is enabled and an interrupt request will be generated
when the Voltage Regulator Ready Interrupt Flag is set.
Bit 2 – B33SRDY BOD33 Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
SAM D5x/E5x Family Data Sheet
SUPC – Supply Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 249