Datasheet

Table Of Contents

• Voltage Regulator Ready (VREGRDY) asynchronous

• BOD33 Ready (BOD33RDY), synchronous

• BOD33 Detection (BOD33DET), asynchronous

• BOD33 Synchronization Ready (B33SRDY), synchronous

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status

and Clear register (INTFLAG) is set when the interrupt condition occurs.

Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable

Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable

Clear register (INTENCLR).

An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.

The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or

the SUPC is reset. See the INTFLAG register for details on how to clear interrupt flags. The user must

read the INTFLAG register to determine which interrupt condition is present.

Note: Interrupts must be globally enabled for interrupt requests to be generated.

19.6.7 Synchronization

The prescaler counters that are used to trigger brown-out detections operate asynchronously from the

peripheral bus. As a consequence, the BOD33 Enable bit (BOD33.ENABLE) need synchronization when

written.

The Write-Synchronization of the Enable bit is triggered by writing a '1' to the Enable bit of the BOD33

Control register. The Synchronization Ready bit (STATUS.B33SRDY) in the STATUS register will be

cleared when the Write-Synchronization starts, and set again when the Write-Synchronization is

complete. Writing to the same register while the Write-Synchronization is ongoing (STATUS.B33SRDY is

'0') will generate a PAC error without stalling the APB bus.

SAM D5x/E5x Family Data Sheet

SUPC – Supply Controller

Datasheet

DS60001507E-page 244