Datasheet

Table Of Contents

18.7 Register Summary

Offset Name Bit Pos.

0x00 CTRLA 7:0 IORET

0x01 SLEEPCFG 7:0 SLEEPMODE[2:0]

0x02

...

0x03

Reserved

0x04 INTENCLR 7:0 SLEEPRDY

0x05 INTENSET 7:0 SLEEPRDY

0x06 INTFLAG 7:0 SLEEPRDY

0x07 Reserved

0x08 STDBYCFG 7:0 FASTWKUP[1:0] RAMCFG[1:0]

0x09 HIBCFG 7:0 BRAMCFG[1:0] RAMCFG[1:0]

0x0A BKUPCFG 7:0 BRAMCFG[1:0]

0x0B Reserved

0x0C PWSAKDLY 7:0 IGNACK DLYVAL[6:0]

18.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the

8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be

accessed directly.

Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC

write protection is denoted by the "PAC Write-Protection" property in each individual register description.

For details, refer to Register Access Protection section.