Datasheet

As example, if the device is in standby sleep mode using the main voltage regulator (MAINVREG) in
low power mode, the voltage level is lower than the one used in active mode. When the device
wakes up, it takes a certain amount of time for the main regulator to transition to the voltage level
corresponding to active mode, causing additional wake-up time.
• Latency due to the CPU clock source wake-up time.
• Latency due to the NVM memory access.
Note: NVM and MAINVREG latencies can be reduced by setting the Fast Wake-Up bits in the
Standby Configuration register (STDBYCFG.FASTWKUP).
Figure 18-3. Total Wake-up Time from Standby Sleep Mode
Low Power mode
PDRAM
active
active
OFF
IRQ from module
WFI instruction
CPU state
run
standby sleep mode
run
interrupt handler
VDDCORE
Main regulator
Main regulator
1
ON
ON
OFF
CLK_CPU
2
3
3
Normal mode
1: latency due to power domain gating
2: latency due to regulator wakeup time
3: latency due to clock source wakeup time
4: latency due to flash memory code access
Main regulator
Normal mode
Related Links
18.6.1.1 Power Domains
18.6.5 DMA Operation
Not applicable.
18.6.6 Interrupts
The peripheral has the following interrupt sources:
• Sleep Mode Entry Ready (SLEEPRDY): indicates that the device is ready to enter standby, hibernate
or backup sleep mode.
This interrupt is a synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the
peripheral is reset.
An interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG register. Each
peripheral can have one interrupt request line per interrupt source or one common interrupt request line
for all the interrupt sources. If the peripheral has one common interrupt request line for all the interrupt
sources, the user must read the INTFLAG register to determine which interrupt condition is present.
SAM D5x/E5x Family Data Sheet
PM – Power Manager
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 223