Datasheet

18.6.4 Advanced Features
18.6.4.1 SleepWalking
SleepWalking is the capability for a device to temporarily wake up clocks for a peripheral to perform a
task without waking up the CPU from STANDBY sleep mode. At the end of the sleepwalking task, the
device can either be woken p by an interrupt (from a peripheral involved in SleepWalking) or enter again
into STANDBY sleep mode. In this device, SleepWalking is supported only on GCLK clocks by using the
on-demand clock principle of the clock sources.
In standby, when SleepWalking is ongoing:
• All the power domains are turned ON including PDRAM power domain.
• The MAINVREG regulator used to execute the sleepwalking task is the selected regulator used in
active mode (LDO or Buck converter). Low power mode of the MAINVREG is not activated during
sleepwalking.
These are illustrated in the figure below.
Figure 18-2. Operating Conditions and SleepWalking
BUCK
LDO
SleepWalking
ACTIVE
RESET
IDLE
RESET
SUPC.
VREG.SEL
LDO
BUCK
Regulator modes
Sleep Mode
STANDBY
HIBERNATE
BACKUP
Sleep modes
IRQ
IRQ
IRQ
RESET
RESET
LDO
(low power mode)
BUCK
(low power mode)
LDO
(low power mode)
BUCK
(low power mode)
LPVREG
Sleep Mode
System RAM
ACTIVE
ACTIVE
ACTIVE
SELECTABLE
0/32KB/FULL
Retention
OFF
Backup RAM
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SELECTABLE
0/4/8KB
Retention
OFF
Regulators are OFF
OFF OFF
PDCORESW
ACTIVE
ACTIVE
ACTIVE
OFF
18.6.4.2 Wake-Up Time
As shown in the figure below, total wake-up time depends on:
• Latency due to Power Domain Gating:
Usually, wake-up time is measured with the assumption that the power domains are already in active
state. When using Power Domain Gating, changing a power domain from OFF to active state will
take a certain time, refer to Electrical Characteristics. If all power domains were already in active
state in standby sleep mode, this latency is zero.
• Latency due to Regulator effect:
SAM D5x/E5x Family Data Sheet
PM – Power Manager
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 222