Datasheet

• Entering Hibernate or Backup mode: This mode is entered by executing the WFI instruction after
selecting the Hibernate or Backup mode by writing the Sleep Mode bits in the Sleep Configuration
register (18.8.2 SLEEPCFG.SLEEPMODE=HIBERNATE or =BACKUP).
• Exiting Hibernate or Backup mode: is triggered when a Hibernate or Backup Reset is detected by the
Reset Controller (RSTC).
Note: In Hibernate mode, the MAINVREG (in low-power mode) regulator is used to allow powering
the PDRAM power domain which can be fully retained according to software configuration.
Note: In Backup mode, the backup regulator (LPVREG) is used, unless VREG.RUNBKUP = 1.
When VREG.RUNBKUP is set, the Main regulator is used in backup mode. The PDBKUPRAM
power domain can be fully retained according to software configuration.
Refer to the 18.6.3.5 Power Domain Controller for the RAM state.
18.6.3.3.4 OFF Mode
In Off mode, the device is entirely powered-off.
• Entering Off mode: This mode is entered by selecting the Off mode in the Sleep Configuration
register by writing the Sleep Mode bits (SLEEPCFG.SLEEPMODE=OFF), and subsequent execution
of the WFI instruction.
• Exiting Off mode: This mode is left by pulling the RESET pin low, or when a power Reset is done.
18.6.3.4 I/O Lines Retention in HIBERNATE or BACKUP Mode
When entering HIBERNATE or BACKUP mode, the PORT is powered off but the pin configuration is
retained. When the device exits the HIBERNATE or BACKUP mode, the I/O line configuration can either
be released or stretched, based on the I/O Retention bit in the Control A register (CTRLA.IORET).
• If IORET=0 when exiting HIBERNATE or BACKUP mode, the I/O lines configuration is released and
driven by the reset value of the PORT.
• If the IORET=1 when exiting HIBERNATE or BACKUP mode, the configuration of the I/O lines is
retained until the IORET bit is written to 0. It allows the I/O lines to be retained until the application
has programmed the PORT.
18.6.3.5 Power Domain Controller
The Power Domain Controller provides several ways of how power domains are handled while the device
is in standby, hibernate or backup mode:
• Standby mode:
When entering standby mode, the PDSYSRAM power domain can be either fully or partially retained
or be fully off according to STDBYCFG.RAMCFG bits. When running sleepwalking task, PDSYSRAM
power domain is active whatever the STDBYCFG.RAMCFG bits are.
• Hibernate mode:
When entering hibernate mode, the PDCORESW power domain is off. As in standby mode, the
PDSYSRAM power domain can be selectively turned ON or OFF by using the HIBCFG.RAMCFG
bits. PDBKUPRAM power domain can be either fully or partially retained or be fully off according to
HIBCFG.BRAMCFG bits. If partial option is selected, only the lowest 4KBytes section is retained
• Backup mode:
When entering backup mode, the PDCORESW and PDSYSRAM power domains are off.
PDBACKUP is still active. As in hibernate mode, PDBKUPRAM power domain can be either fully or
partially retained or be fully off according to BKUPCFG.BRAMCFG bits.
• OFF mode:
When entering OFF mode, all the power domains are off.
The table below illustrates the PDRAM state:
SAM D5x/E5x Family Data Sheet
PM – Power Manager
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 219