Datasheet

Note:
1. Running if requested by peripheral during SleepWalking
2. Running during SleepWalking
18.6.3.3.1 IDLE Mode
IDLE mode allows power optimization with the fastest wake-up time.
The CPU is stopped, and peripherals are still working. As in Active mode, the AHBx and APBx clocks for
peripheral are still provided if requested. As the main clock source is still running, wake-up time is very
fast.
• Entering Idle mode: The Idle mode is entered by executing the WFI instruction. Additionally, if the
SLEEPONEXIT bit in the Cortex System Control register (SCR) is set, the Idle mode will be entered
when the CPU exits the lowest priority ISR (Interrupt Service Routine, refer to the ARM Cortex
documentation for details). This mechanism can be useful for applications that only require the
processor to run when an interrupt occurs. Before entering the Idle mode, the user must select the
Idle Sleep mode in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=IDLE).
• Exiting Idle mode: The processor wakes the system up when it detects any non-masked interrupt
with sufficient priority to cause exception entry. The system goes back to the Active mode. The CPU
and affected modules are restarted.
GCLK clocks, regulators and RAM are not affected by the Idle Sleep mode and operate in normal mode.
18.6.3.3.2 STANDBY Mode
The STANDBY mode is the lowest power configuration while keeping the state of the logic and the
content of the RAM.
In this mode, all clocks are stopped except those configured to be running sleepwalking tasks. The clocks
can also be active on request or at all times, depending on their on-demand and run-in-standby settings.
Either synchronous (CLK_APBx or CLK_AHBx) or generic (GCLK_x) clocks or both can be involved in
sleepwalking tasks. This is the case when for example the SERCOM RUNSTDBY bit is written to '1'.
• Entering STANDBY mode: This mode is entered by executing the WFI instruction after writing the
Sleep Mode bit in the Sleep Configuration register (18.8.2 SLEEPCFG.SLEEPMODE=STANDBY).
The SLEEPONEXIT feature is also available as in IDLE mode.
• Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake up the
system. For example, a peripheral running on a GCLK clock can trigger an interrupt. When the
enabled asynchronous wake-up event occurs and the system is woken up, the device will either
execute the interrupt service routine or continue the normal program execution according to the
Priority Mask Register (PRIMASK) configuration of the CPU.
Refer to the section about the Power Domain Controller for the RAM state.
The regulator operates in low-power mode by default and switches automatically to the normal mode in
case of a sleepwalking task requiring more power. It returns automatically to low power mode when the
sleepwalking task is completed.
Related Links
18.6.3.5 Power Domain Controller
18.6.3.3.3 Hibernate and Backup Mode
Hibernate and Backup mode allow achieving the lowest power consumption aside from OFF. The device
is entirely powered off except for the backup domain. All peripherals in backup domain are allowed to run,
for example, the RTC can be clocked by a 32.768 kHz oscillator. All PM registers are retained except
INTENCLR, INTENSET, INTFLAG, and SLEEPCFG registers.
SAM D5x/E5x Family Data Sheet
PM – Power Manager
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 218