Datasheet

17.8.1 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 7 6 5 4 3 2 1 0
DUALE SINGLEE
Access
R/W R/W
Reset 0 0
Bit 1 – DUALE Dual Bit Error Interrupt Enable Clear
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Dual Bit Error Interrupt Enable bit, which disables the Dual Bit Error
interrupt.
Value Description
0
The Dual Bit Error interrupt is disabled.
1
The Dual Bit Error interrupt is enabled.
Bit 0 – SINGLEE Single Bit Error Interrupt Enable Clear
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Single Bit Error Interrupt Enable bit, which disables the Single Bit Error
interrupt.
Value Description
0
The Single Bit Error interrupt is disabled.
1
The Single Bit Error interrupt is enabled.
SAM D5x/E5x Family Data Sheet
RAMECC – RAM Error Correction Code (ECC)
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 208