Datasheet

56.8.5 Fractional Digital Phase Lock Loop (FDPLL) Characteristics (125°C)
Table 56-28. Fractional Digital Phase Lock Loop Characteristics
(1)
Symbol Parameter Conditions Min. Typ. Max. Units
Jp Period jitter (Peak-Peak value) f
IN
= 32 kHz, f
OUT
= 96 MHz - 1.9 3.0 %
f
IN
= 32 kHz, f
OUT
= 200 MHz - 3.4 6.0
f
IN
= 3.2 MHz, f
OUT
= 96 MHz - 2.0 3.1
f
IN
= 3.2 MHz, f
OUT
= 200 MHz - 4.3 7.2
Note:
1. These FDPLL200M characteristics are applicable with LDO regulator and a direct reference (i.e.,
REFCLK is XOSC or XOSC32K, not GCLK).
Table 56-29. Power Consumption
Symbol Parameter Conditions TA Typ. Max. Units
I
DD
Current Consumption Ck = 96 MHz, VDD = 3.3V Max. 125°C
Typ. 25°C
0.9 2.5 mA
Ck = 200 MHz, VDD = 3.3V 2.0 3.4
56.9 Timing Characteristics (125°C)
56.9.1 SERCOM in SPI Mode Timing (125°C)
Table 56-30. SPI Timing Characteristics and Requirements
(1)
Symbol Parameter Conditions Min. Typ. Max. Units
t
MIS
MISO setup to SCK Master, VDD>2.70V 19.5 - - ns
Master, VDD>1.71V 20 - -
t
SOV
MISO output valid SCK Slave, VDD>2.70V 16.5 - - ns
Slave, VDD>1.71V 25 - -
1. These values are based on simulation, with capacitance load between 5pF and 20pF. These values
are not covered by test limits in production.
SAM D5x/E5x Family Data Sheet
Electrical Characteristics at 125°C
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 2071