Datasheet

Table 56-5. Active Current Consumption - Active Mode
Mode conditions Regulator Clock VDD T
A
Typ. Max. Units
ACTIVE COREMARK
(1)
LDO
FDPLL 100 MHz
1.8
Max. at 125°C Typ at 25°C
136 229
uA/Mhz
3.3 137 232
DFLL 48 MHz
1.8 136 370
3.3 136 371
XOSC 32 MHz
1.8 146 611
3.3 149 613
BUCK
FDPLL 120 MHz
1.8 103 215
3.3 65 176
DFLL 48 MHz
1.8 102 324
3.3 63 242
XOSC 32 MHz
1.8 110 505
3.3 73 370
IDLE NA
LDO
FDPLL 100 MHz
1.8 21 114
3.3 23 116
DFLL 48 MHz
1.8 21 252
3.3 21 252
XOSC 32 MHz
1.8 25 367
3.3 27 371
BUCK
FDPLL 100 MHz
1.8 16 89
3.3 11 78
DFLL 48 MHz
1.8 16 194
3.3 10 147
XOSC 32 MHz
1.8 21 287
3.3 19 223
Note:
1. System Configuration used:
– MCLK all APB clocks masked except MCLK and NVMCTRL
– MCLK.AHBMASK = 0x00C00FFF
– CMCC enabled
SAM D5x/E5x Family Data Sheet
Electrical Characteristics at 125°C
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 2056